The unintended discharge of electronic circuitry is one of the most common causes of damage to board test systems. Often, a loaded printed circuit board being tested will have been powered up previously at some other point in the manufacturing process. An example of this situation is a printed circuit board that fails functional test or hot mockup and then is returned to board test for trouble-shooting.
Charge often remains on a capacitive component long after the source of power has been removed. If the board test system makes connection to the device under test (DUT) in such a way as to short out a charged capacitive element, much of the energy stored on that element is dissipated in the test system's relay contacts. The typical result of this situation is a welded relay causing a defect in the test system with associated increased warranty costs.
Current test systems discharge printed circuit board electronic circuitry through one of several different resistors located in the test system. The chosen resistor must be large enough to limit the current through the connecting relays to a safe level. The current approach is relatively slow. The discharge rate is determined by the time constant formed by the discharge resistor and the capacitance of the device under test. The resistor must be large enough to limit the discharge current to a safe level under worst case voltage conditions. The magnitude of the discharge current decreases as the capacitor is discharged. As such, the discharge rate is not as fast as could be obtained if a constant current were used. So to speed things up, lower valued resistors are switched in as the voltage at the terminals of the electronic circuitry decreases. However, the time necessary to switch in the smaller resistors is not insignificant.
In addition, the very act of discharging a capacitive element of the electronic circuitry of the printed circuit board may recharge a capacitive element of the electronic circuitry that had been previously discharged. As an example, consider a printed circuit board having three capacitors that are connected in a delta network with each capacitor containing some charge and with each connection point between two of the capacitors being a test point. One of the capacitors in the delta network can be discharged such that the voltage across the capacitor and the charge held by it are reduced to zero. The voltage across the series combination of the other two capacitors is also zero. But, the voltage and the charge on each to the series combination capacitors taken individually is not. If a second capacitor in the delta network is subsequently discharged, the voltage and charge on this capacitor will be forced to zero. But, some of the charge on the third capacitor will be transferred back to the first capacitor, i.e., to the capacitor that had previously been discharged. Because of the “charge transfer” problem just described, it may be necessary to repeat the discharge cycle until all capacitors are found to be at a safe voltage level.
In order to discharge a particular device under test in a reasonable length of time, it may be necessary to limit the discharge to only those nodes capable of damaging the test system. In some test systems, as for example the Agilent 3070, a software program analyzes capacitor sizes and power supply voltages to determine which capacitors need to be discharged and which do not. The accuracy of this analysis is dependant upon the accuracy of data entered by the customer and whether or not the customer consistently updates the data as changes are made in the board's design. This process is quite prone to error, and if the customer makes a mistake, the test system manufacturer often pays for damage to the test system, either through higher warranty costs or in the higher cost of providing a service contract. In addition, this method is complex. The test system manufacturer must write and support a great deal of software in providing this feature. In addition, the customer must be trained in how to use this feature and must spend time supporting it whenever a change is made to the printed circuit board design.